B. Kuo, “Floating-Muscles Kink-Perception Related Capacitance Conclusion of Nanometer PD SOI NMOS Devices” , EDMS , Taiwan

71. G. S. Lin and you can J. B. Kuo, “Fringing-Triggered Thin-Channel-Feeling (FINCE) Associated Capacitance Choices away from Nanometer FD SOI NMOS Gadgets Having fun with Mesa-Isolation Thru three-dimensional Simulation” , EDSM , Taiwan ,

72. J. B. Kuo, “Evolution from Bootstrap Approaches to Low-Voltage CMOS Digital VLSI Circuits for SOC Software” , IWSOC , Banff, Canada ,

P. Yang, “Gate Misalignment Feeling Relevant Capacitance Behavior out of a good 100nm DG FD SOI NMOS Device having letter+/p+ Poly Most readily useful/Base Door” , ICSICT , Beijing, Asia

73. Grams. Y. Liu, Letter. C. Wang and you will J. B. Kuo, “Energy-Efficient CMOS Higher-Weight Rider Circuit into the Complementary Adiabatic/Bootstrap (CAB) Way of Low-Energy TFT-Lcd Program Software” , ISCAS , Kobe, The japanese ,

74. Y. S. yasal posta sipariЕџi gelin Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Trend out of 100nm FD SOI CMOS Devices that have HfO2 High-k Door Dielectric Offered Vertical and you will Fringing Displacement Effects” , HKEDSSC , Hong kong ,

75. J. B. KUo, C. H. Hsu and you can C. P. Yang, “Gate-Misalignment Associated Capacitance Choices out-of a good 100nm DG SOI MOS Gizmos with N+/p+ Top/Base Gate” , HKEDSSC , Hong-kong ,

76. Grams. Y. Liu, Letter. C. Wang and you may J. B. Kuo, “Energy-Effective CMOS High-Weight Driver Routine towards the Complementary Adiabatic/Bootstrap (CAB) Technique for Reasonable-Electricity TFT-Liquid crystal display Program Programs” , ISCAS , Kobe, Japan ,

77. H. P. Chen and you can J. B. Kuo, “An effective 0.8V CMOS TSPC Adiabatic DCVS Reasoning Circuit towards the Bootstrap Techniques getting Reasonable-Fuel VLSI” , ICECS , Israel ,

B. Kuo, “A novel 0

80. J. B. Kuo and you can H. P. Chen, “The lowest-Current CMOS Weight Rider towards the Adiabatic and Bootstrap Strategies for Low-Energy Program Applications” , MWSCAS , Hiroshima, Japan ,

83. Meters. T. Lin, Age. C. Sunlight, and you will J. B. Kuo, “Asymmetric Door Misalignment Affect Subthreshold Attributes DG SOI NMOS Equipment Provided Fringing Digital Field-effect” , Electron Equipment and you can Procedure Symposium ,

84. J. B. Kuo, Age. C. Sunshine, and you can Meters. T. Lin, “Studies regarding Gate Misalignment Affect the latest Endurance Voltage out of Double-Door (DG) Ultrathin FD SOI NMOS Gizmos Having fun with a concise Model Given Fringing Digital Field-effect” , IEEE Electron Products having Microwave and Optoelectronic Software ,

86. E. Shen and you can J. 8V BP-DTMOS Articles Addressable Thoughts Mobile Routine Based on SOI-DTMOS Process” , IEEE Meeting to your Electron Gadgets and Solid-state Circuits , Hong-kong ,

87. P. C. Chen and you will J. B. Kuo, “ic Logic Circuit Playing with a direct Bootstrap (DB) Way of Reasonable-current CMOS VLSI” , International Symposium on Circuits and you may Expertise ,

89. J. B. Kuo and S. C. Lin, “Lightweight Malfunction Model getting PD SOI NMOS Gizmos Given BJT/MOS Impact Ionization to own Spice Circuits Simulation” , IEDMS , Taipei ,

ninety. J. B. Kuo and you may S. C. Lin, “Lightweight LDD/FD SOI CMOS Unit Design Offered Time Transportation and you may Notice Temperature to have Spruce Circuit Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you will J. B. Kuo, “Fringing-Created Burden Lowering (FIBL) Ramifications of 100nm FD SOI NMOS Gizmos with a high Permittivity Door Dielectrics and you may LDD/Sidewall Oxide Spacer” , IEEE SOI Appointment Proc , Williamsburg ,

ninety-five. J. B. Kuo and you can S. C. Lin, “The fresh new Fringing Digital Field-effect towards the Short-Channel Impact Endurance Voltage away from FD SOI NMOS Gadgets that have LDD/Sidewall Oxide Spacer Build” , Hong kong Electron Gizmos Meeting ,

93. C. L. Yang and you will J. B. Kuo, “High-Temperatures Quasi-Saturation Make of Highest-Current DMOS Power Devices” , Hong kong Electron Equipment Meeting ,

94. Elizabeth. Shen and you can J. B. Kuo, “0.8V CMOS Stuff-Addressable-Thoughts (CAM) Phone Ciurcuit that have an easy Tag-Contrast Functionality Using Bulk PMOS Active-Tolerance (BP-DTMOS) Techniques Predicated on Fundamental CMOS Technology having Reasonable-Current VLSI Possibilities” , Around the globe Symposium towards the Circuits and you may Options (ISCAS) Proceedings , Washington ,

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